Tracked shipping to South Africa with premium packaging for just R199 

Ship to
South Africa
0

My Account

  • argentina
  • chile
  • colombia
  • españa
  • méxico
  • perú
  • estados unidos
  • internacional

menu

Select your country

Americas

Europe

Rest of the world

portada High-Level Verification: Methods and Tools for Verification of System-Level Designs
Type
Physical Book
Author
Publisher
Language
English
Pages
167
Format
Paperback
Dimensions
23.4 x 15.6 x 1.0 cm
Weight
0.27 kg.
ISBN13
9781493901012
Categories

High-Level Verification: Methods and Tools for Verification of System-Level Designs

Rajesh K. Gupta (Author) · Sudipta Kundu (Author) · Sorin Lerner (Author) · Springer · Paperback

High-Level Verification: Methods and Tools for Verification of System-Level Designs - Kundu, Sudipta ; Lerner, Sorin ; Gupta, Rajesh K.

Cheaper New Book Imported to South Africa
Delivery: 21 Jul - 18 Aug Shipping: 12 to 16 business days.
R 1,709
Faster New Book Imported to South Africa
Delivery: 09 Jul - 03 Aug Shipping: 4 to 5 business days.
R 2,299
R 1,709

Choose the list to add your product or create one New List

Go to My Wishlists
Calculate shipping cost

Synopsis "High-Level Verification: Methods and Tools for Verification of System-Level Designs"

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

Customers reviews

More customer reviews
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)
  • 0% (0)

Frequently Asked Questions about the Book

Is the book original?

All books in our catalog are Original.

In what language is the book written?

The book is written in English.

What is the format of this book?

The binding of this edition is Paperback.

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews