Synopsis "Design and performance analysis of low power and high speed dual modulus prescalers"

The broadband wireless communications extensively use high-performance synthesizers. To achieve flexible frequency synthesis, the two essential components namely Voltage Controlled Oscillator (VCO) followed by the frequency divider must be power efficient and operate at high frequency. The frequency divider is a basic block in a Phase Lock Loop (PLL) synthesizer for the conversion from high to low frequencies. Prescaler is one of the most vital parts of frequency-divider as it works at high speed and consumes maximum power. The objective of this research work is to design divide by 'N' prescaler and divide by N/N+1 dual modulus prescalers for various low power applications. In this thesis, we have carried a detailed analysis on the speed and power consumption of the digital dividers. We performed design and implementation of low power divide by 'N' prescalers. Architecture of the divide by 'N' prescalers using hybrid master slave flip flop has been explained. Based on this architecture divide by 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 prescaler circuits have been successfully designed at 5 GHz operating frequency.

Customers reviews

Have you read this book? Login to add your review.

More customer reviews

0% (0)
0% (0)
0% (0)
0% (0)
0% (0)

Questions and Answers about the Book

Do you have a question about the book? Login to be able to add your own question.

Opinions about Bookdelivery

More customer reviews

Design and performance analysis of low power and high speed dual modulus prescalers - Nirmal, Uma ; Jain, V. K.

Synopsis "Design and performance analysis of low power and high speed dual modulus prescalers"

Customers reviews

Frequently Asked Questions about the Book

Is the book original?

In what language is the book written?

What is the format of this book?

Questions and Answers about the Book

Opinions about Bookdelivery