verification presents the most time-consuming task in the integrated circuit design process. the increasing similarity between implementation verification and the ever-needed task of providing vectors for manufacturing fault testing is tempting many professionals to combine verification and testing efforts. this book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. the book brings the results in the direction of merging manufacturing test vector generation and verification. it first discusses error fault models suitable for approaching the verification by testing methods. then, it elaborates a proposal for an implicit fault model that uses the arithmetic transform representation of a circuit and the faults. presented is the fundamental link between the error size and the test vector size, which allows parametrizable verification by test vectors. furthermore, the test vector set is sufficient not only for detecting, but also for diagnosing and correcting the design errors. the practical use of any such simulation-based verification scheme can be seriously impaired by redundant faults, that otherwise require exhaustive simulations. the redundant fault identification methods are presented that are well suited for the type of faults considered. finally, the same representation can be used to augment and expand the formal verification schemes that are to be used in conjunction with the simulation-based verification. the primary audience for verification by error modeling includes researchers in verification and testing, managers in charge of verification of test and practicing engineers. due to its comprehensive coverage of background topics, the book can also be used for teaching courses on verification and test topics.
